A Compiler Target Model for Line Associative Registers

Line Associative Registers (LARs) are the basis for a new class of processor architectures in which memory accesses are minimized by explicitly managing wide lines of instructions and data in processor registers. The design of LARs has signi cant commonality with a number of existing technologies which have been more or less widely adopted, however, we rmly believe that LARs-based design, which will employ a highly unusual execution model discussed in the remainder of this paper, has ever increasing potential for performance gains over conventional designs utilizing hierarchies of caches and registers. In order to e ectively test and utilize this new design, suitable development tools must be written. This paper attempts to describe the implications of a LARs-based architecture for compiler writers, and demonstrate that the bene ts of such a design can be harnessed with the use of conventional programming languages. At this time, a HDL veri cation model implementing a simple LARs-based architecture has been completed, and progress has begun on developing a set of software development tools based on the LLVM compiler infrastructure is underway.